70 * ( 10ns ) + .30 * ( 100ns ) = 37ns average access time
3.13 Assume our 1GHz computer, which averages 3 cycles per instruction, is connected to the Internet via
a 10 Mbit connection (i.e., the line speed allows 10 million bits to pass every second). From the time
the computer receives the first bit, how many instructions can the computer execute while waiting for
a single 8-bit character to arrive?
8 bits * 1 sec./10,000,000 bits = .0000008 sec./character
1Billion cycles/sec. * 1 instruction/3 cycles * .0000008
sec./character = 267 instr/char
3.14 What complexity does DMA present to the management of cache memory?
DMA directly updates main memory, or directly reads from main memory. If the CPU takes
advantage of cache memory to accelerate reads and writes, a ???cache coherency??? can develop.
The CPU may be reading memory location x via a cached copy that has been changed in main
memory via a DMA transfer. The cached value is, therefore, ???stale.??? Likewise, if DMA is being
used to write values from main memory to a device, and values the CPU has written to cache
memory have not yet been ???flushed??? to main memory, stale or incorrect values may be written.
186 ANSWERS TO REVIEW QUESTIONS
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